The Gateway to Computer Science Excellence
0 votes
221 views
Consider a 5 stage pipeline with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Write Back (WB) and Memory Access (MA) having latencies (in ns) 3,8, 5, 6 and 4 respectively. What is average CPl of non-pipeline CPU when speed up achieved by to pipeline is 4?
A. 1.33
B. 1.76
C. 1.14
D. 1.66
in CO and Architecture by Active (4.5k points)
closed by | 221 views

Related questions

Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
50,650 questions
56,208 answers
194,073 comments
95,108 users