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Consider a 5 stage pipeline with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Write Back (WB) and Memory Access (MA) having latencies (in ns) 3,8, 5, 6 and 4 respectively. What is average CPl of non-pipeline CPU when speed up achieved by to pipeline is 4?
A. 1.33
B. 1.76
C. 1.14
D. 1.66
in CO and Architecture by Active (4.5k points)
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