ACE CBT 2018

Question

An instruction pipelined processor has five stages namely, instruction fetch (F), instruction decode
(D), Instruction execution (E), memory Access for operand (M) and write Back (W) with stage
latencies of 1 ns, 2ns, 2 ns, 1 ns, 1 ns respectively. To gain interms of frequency, the designer
decided to split the decoder stage into two stages D1 and D2 each of latency 1 ns and execute stage
into 3 stages E1, E2 and E3 stages each of latency 2ns/3.
A program has '100' instructions, all instructions use all stage services. The amount of time saved
(in ns) using new design over old design is __________.

I am getting 99 but the answer provided is 96. Can you please verify.

Comments

https://gateoverflow.in/3805/gate2005-it-44

Have a look.

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@prashant jha 1 i remember solving a previous gate problem which was a of numeric where they awarded marks for the above mentioned method which you used and for the method i used. i will link it if i find.

BUT i still think the first iteration needs only 7ns because it need not wait for execution of any stage. 

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https://gateoverflow.in/1063/gate2004-69

I think you were referring this.. @OneZero but we have to take @prashant jha 1 saying

Answer 1

Old design:

K = 5, tp= max (1, 2 ,2, 1, 1)=2 ns ,n = 100

Execution time = (k+n-1)x tp  = (5 + 100-1) × 2 = 208 ns

 

New design:

K = 8, tp= max (1, 1, 1, 2/3, 2/3 2/3, 1,1 ) =1 ns

Execution time = (k+n-1)x tp  = (8 + 100-1) × 1 = 107 ns

Amount of time saved = (208 – 106) = 101 ns

Hence final answer should be 101 ns.