An instruction pipelined processor has five stages namely, instruction fetch (F), instruction decode
(D), Instruction execution (E), memory Access for operand (M) and write Back (W) with stage
latencies of 1 ns, 2ns, 2 ns, 1 ns, 1 ns respectively. To gain interms of frequency, the designer
decided to split the decoder stage into two stages D1 and D2 each of latency 1 ns and execute stage
into 3 stages E1, E2 and E3 stages each of latency 2ns/3.
A program has '100' instructions, all instructions use all stage services. The amount of time saved
(in ns) using new design over old design is __________.
I am getting 99 but the answer provided is 96. Can you please verify.