MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory

Consider a 2 way set associative cache with 4 blocks. The memory block requests in the order.4,6,3,8,5,6,0,15,6,17,20,15,0,8If LRU is used for block replacement then memo...

snaily16

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snaily16 asked Jan 28, 2019

CO and Architecture
co-and-architecture
cache-memory
made-easy-test-series

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0 votes

1 answer

Prateek Raghuvanshi asked Dec 22, 2018

1,007 views

MadeEasy Full Length Test 2018: CO & Architecture - Cache Memory
Consider the following cache A and B .let the average access times in cache A and B is $t_A$ and $t_B$ respectively.the value of $t_A+t_B$ _(in ns) Answer is given as 30.18 ns I am getting 31.2 ns .Please verify it .

Consider the following cache A and B .let the average access times in cache A and B is $t_A$ and $t_B$ respectively.the value of $t_A+t_B$ _(in ns)Answer is given as 30.1...

Prateek Raghuvanshi

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Prateek Raghuvanshi asked Dec 22, 2018

CO and Architecture
co-and-architecture
cache-memory
made-easy-test-series

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4 votes

1 answer

Ram Swaroop asked Jan 30, 2019

1,562 views

MadeEasy Test Series 2019: CO & Architecture- Cache Memory
Consider a n-way cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory required for tags is 1024 bytes. What will be the values of n and x respectively? Answer 256 512

Consider a n-way cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory re...

Ram Swaroop

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Ram Swaroop asked Jan 30, 2019

CO and Architecture
co-and-architecture
cache-memory
made-easy-test-series

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5 votes

1 answer

Ram Swaroop asked Jan 29, 2019

1,257 views

MadeEasy Test Series 2019: CO & Architecture - Cache Memory
A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time of L1 and L2 are 5 and 10 clock cycles and penalty for L2 cache miss to main memory is 70 clock cycles. The average memory access time will be

A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time o...

Ram Swaroop

1.3k views

Ram Swaroop asked Jan 29, 2019

CO and Architecture
co-and-architecture
cache-memory
made-easy-test-series

+ –

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