ME Test series question

Question

A computer uses two level cache L1 and L2 and in 2000 memory references there are 320 misses in L1 cache and 150 misses in L2lcache. If the miss penalty of L2 is 300 clock cycles, hit time of L1 is 1 clock cycle and hit time of L2 is 10 clock cycles what is the average memory access time?

Comments

I am getting 25.1 cycle .

Tavg = $1+\frac{320}{2000}*10 +\frac{320}{2000}*\frac{150}{320}*300=25.1 cycle$

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seems correct

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https://gateoverflow.in/293415/effective-access-time 

same

 

Answer 1

25.1 Cycle