Consider the unpipelined machine with $10$ nanoseconds clock cycles. It uses four cycles for ALU operations and branch whereas 5 cycles for memory operation. Assume that the relative frequencies of these operations are $40\%, 20\%,$ and $40\%$ respectively. Suppose that due to clock skew and setup, pipelining the machine adds $1$ nanosecond overhead to the clock. _____________ times speed up in the instruction execution rate is gained from a pipeline.
