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A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time of L1 and L2 are 5 and 10 clock cycles and penalty for L2 cache miss to main memory is 70 clock cycles. The average memory access time will be

 

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(1140*5 + 30*15 + 30*85) /1200 = 7.25
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Hi @balchandar reddy san , can you kindly help me with the understanding of the question , I kinda didn't understand it much . Thanks :)

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5.5875?
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Please check the answer..

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There are in total 1200 references,

No. of hits in L1 : 1200-60 = 1140, so L2 will be referenced 60 times out of which 30 are misses in L2

No. of hits in L2 : 60-30, so MM will be referenced 30 times.

Access time for 1200 references:1140*acesstime(L1) + 60* acesstime(L2+L1) + 30*acesstime(MM+L2+L1)

Average access time: 1140*acesstime(L1) + 60* acesstime(L2+L1) + 30*acesstime(MM+L2+L1) / 1200

 

(OR)
 

L1 will be referenced 1200 times, (hit + miss)

L2 will be referenced 60 times, (hit + miss)

MM will be referenced 30 times, (hit)

Access time for 1200 references: 1200*acesstime(L1) + 60*acesstime(L2) + 30*acesstime(MM)

Average access time: 1200*acesstime(L1) + 60*acesstime(L2) + 30*acesstime(MM) / 1200
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I understood your solution , thanks .

The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory reference

 

I was confused because of this line , the word "penalty" doesn't fit here suitably. Frequency and penalty don't have the same inference right? 

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Thanks @balchandar reddy san
Nice explanation
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