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A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size of cache is increased from one word to four words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____
(Upto 2 decimal places)
in CO and Architecture by Active (1.7k points)
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getting 1.31 . what's the answer?
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I am getting 1.55.

$\frac{0.148 * 9}{0.026*33}$
0

 

what to do about this??

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@prashant jha 1 what was your approach?

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