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Consider the cache memory size of 16kb, and cache block size is 16 bytes. The processor generates the physical address of 32 bits. Assume the cache is fully associative. What are the TAG and index bits __________

(A) 28 and 4bits

(B) 28 and 0bits

(C) 24 and 4bits

(D) 24 and 0bit

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Block size= 16B = 2^4 which means 4bits for indexing , remaining (32-4) =28 bits for Tag

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