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closed as a duplicate of: GATE CSE 2019 | Question: 1
Consider the cache memory size of 16kb, and cache block size is 16 bytes. The processor generates the physical address of 32 bits. Assume the cache is fully associative. What are the TAG and index bits __________

(A) 28 and 4bits (B) 28 and 0bits (C) 24 and 4bits (D) 24 and 0bits
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For Fully Associative Mapping:

 There is no index bits  in fully associative mapping,hence Index bits = 0

number of bits in block offset = ceil(log2 Cache block size) = ceil(log2 16) = 4

As physical address is 32 bits

Number of Tag bits = 32-4 = 28 

So  B is the answer

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