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A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the starting address of the block, it then takes $3$ cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of $1$ word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is  ______$\times 10^6$ bytes/sec

edited | 4k views
+10
I got 160.

On miss it require total 12 clock cycle.

And 1 clock cycle cost is $\frac{1}{60}$ micro sec. So for 12 clock cycle it would require 0.2 micro second. Which means on 1 miss it require a total of 0.2 micro second in which 32 byte of data can be transmitted. So in 1 sec it can transmit $160×10^6$ Byte of data, which is its bandwidth.
+1
Yes ans should be 160.
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Bandwidth for a memory system = $\frac{Bytes Transferred}{cycle time}$
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Bandwidth = data rate (they even gave the units)

Bytes = 32

Time = 1 + 3 + 8(1) cycles.

1 cycle = $\frac{1}{60*10^6}$ seconds.

So, bandwidth = $\frac{32*60*10^6}{12}$

So, 160

Time to transfer a cache block $= 1+3+8 = 12$ cycles.

i.e., $4$ bytes $\times 8 = 32$ bytes in $12$ cycles.

So, memory bandwidth $= \frac{32}{12 \text{ cycle time}} =\frac{32}{12/(60 \times 10^6)}= 160 \times 10^6$ bytes/s
by Veteran (436k points)
selected
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Sir when block has came into cache

Only one word should be fetched why we are accessing whole block while the address request is of word not block.

1+3+1 = 5 cycles should be delay.

Which gives ans 384.

@Arjun sir plz confirm

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@Arjun Sir I got 160.06 as the answer. Will it be considered as correct. The thing is I did 60MHz =(1/60)*10^6 second which is 0.01666 *10^6 seconds . So the calculation would be 160.06 *10^6 bytes/ second. Will there be a range for this answer.

+2
Block is the smallest unit of transfer between main memory and cache. Word is between cache and CPU.

Regarding range -- it depends on those making official key. They might give a range.
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here we have to fetch all 8words completely which could be done in 8cycles(total at once),not to considered as single cycle every time.
+6

This question was asked from this NPTEL video from IIT-Madras from the concept taught at $42:00$ onwards. Interestingly paper of 2019 was also set by the IITM.

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@sandeepn96 was that considered?

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@JEET GATE paper is not set by the organizing institute. It's set by the GATE committee consisting of professors from all IITs.

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@Arjun question says " maximum bandwidth for the memory system when the program running on the processor issues a series of read operations ". So in case of maximum bandwidth, shouldn't we consider a case of no miss in cache. In that case, i word that is 4 bytes will be transferred in 1 clock cycle. Therefore BW should be 240 in that case. Please correct me.
$\underline{\mathbf{Answer:}}\;\bbox[lightgreen, 5px, border: 2px solid black]{\color {black} {160 \times 10^6\; \frac{\mathrm {Bytes}}{\mathrm{sec}}}}$

$\underline{\mathbf{Explanation:}}$

$\text {Given frequency} = 60\ \text{MHz}$

This means that the processor completes $\color{green}{60\times 10^6 \;\text{cycles in}\;1 \;\text{second}}.$

$\therefore$ One cycle is completed in $\dfrac{1}{60\times 10^6 }\; \text{seconds}$

Now,

To service a cache miss, number of cycles needed $= 1\;\text{cylce}\;\color{blue}{\text{(to accept starting address of the block)}} + 3\;\text{cylces}\;\color{blue}{\text{(to fetch all the$8$words of the blocks)}} + \underbrace{8\times1}_\text{$\because$1 word per cycle}\;\text{cylces}\;\color{blue}{\text{(to transmit all$8$words of the block)}}= 12 \;\text{cycles}$

$\mathbf{Note:}$ Total data is the data which is used for trasmitting the words of the requested block at the rate of $\mathbf{1}$ word per cycle $=\mathbf{8\;words \times 4\;Byte\;(Size\; of\; each\; word)}$

\begin{align}\therefore \mathbf{Bandwidth} \require{cancel} &= \dfrac{\text{Total Data}}{12 \;\text{cycle time}} \\&= \dfrac{8\times4\;\text{Bytes}}{12\;\text{cycles }\times1\; \text{cycle time}} \\&= \dfrac{32}{12 \times \dfrac{1}{60\times10^6}} \\&= \require{cancel} \dfrac{32\times \cancel {60}^{5} \times 10^6}{\cancel{12}^1}\\& = 5 \times 32 \times {10}^6 \\&= \color {black}{160 \times 10^6 \; \dfrac{\text{Bytes}}{\mathrm{sec}}}\end{align}

$\therefore \bbox[lightgreen, 5px, border: 2px solid black]{\color {black}{160 \times 10^6 \; \dfrac{\text{Bytes}}{\mathrm{sec}}}}$ is the correct answer.
by Boss (19.7k points)
edited by
ans should be 160
by Junior (633 points)
by (221 points)
0
How can you explaine
$Cache\ block = 8\ words$

$Word\ size = 4\ bytes$

$Cache\ block\ size = 32\ bytes$

$frequency = 60\ MHz$

$Cycle\ time(\#\ of seconds/cycle) = \dfrac{1}{frequency} = \dfrac{1}{60×10^6} seconds$

$Cache\ miss\ time:$

$1\ cycle(Address\ of\ the\ block)$

$3\ cycles (fetch\ all\ the\ 8-words\ of\ the\ block)$

$8\ cycles (transfer\ of\ 8-words\ at\ the\ rate\ of\ 1\ cycle/word )$

$Total = 12\ cycles$

$Total\ time= \dfrac{12}{60×10^6}sec$

$Total\ bandwidth = \dfrac{total\ data}{total\ time} = \dfrac{32\ bytes}{\dfrac{12}{60×10^6}} = 160 × 10^6 bytes/second$

$Answer: 160$
by Loyal (6k points)
edited
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Just edit it little more.

From bottom $3^{rd}$ lin is $10^6$
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Done editing.

Thank you.
+1 vote
total number of cycles = 1 + 3 + 8 = 12

total data transferred = 8 words * 4 bytes per word = 32 bytes

frequency of clock = 60 MHz

so bandwidth = total data transferred/total time taken

= 32  bytes/(12cycles/(60*10^6cycles per sec))

= 160 * 10 ^ 6 bytes/sec

It is maximum in the case when every read request is a cache miss.
by Active (2.1k points)
+1 vote
$T=1/60\ \mu s\ per\ cycle$

TOTAL no of cycles required to transfer 1 cache block of size 32 Bytes is

= 1+3+1*8

= 12 cycles

TOTAL time taken in case of cache miss =12*1/60 $\mu s$

= 0.2 $\mu s$

Now, Bandwidth = 32/0.2 * $10^6$B per sec

= 160 * $10^6$ B/s

Note here that we are considering the max bandwidth from main memory to cache which happens only when there is a cache miss and not from cache to processor.
by Boss (10.9k points)
Cache block = 8 words
Word size = 4 bytes
Cache block size = 32 bytes
Clock = 60 MHz
⇒ T = 1/clock = 1/60×10^6 seconds
Cache miss
= 1 cycle(Address) + 3 cycles (8 words) + 1word/cycle ×8 (transfer)
= 12 cycles
= 12/60×10^6
Total bandwidth = total data/total time = 32 bytes/(12/60×10^6) = 160 × 10^6 bytes/second
by Junior (599 points)
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I am getting answer  as 166 bytes per second. First convert 60 mega Hertz as 1 /(60*10^6). = 16 nsec .To fetch a block from main memory it requires 12 clock cycles

12×16nsec = 192 nsec

In 192 nsec 32 bytes are transferred so in one second 32/(192 ×10^(-9))

166 × 10 ^(6) bytes per second

Is 166 right.?