GATE CSE 2019 | Question: 45

Question

A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the starting address of the block, it then takes $3$ cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of $1$ word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is  ______$\times 10^6$ bytes/sec.

Comments

Bandwidth = data rate (they even gave the units)

Bytes = 32

Time = 1 + 3 + 8(1) cycles.

1 cycle = $\frac{1}{60*10^6}$ seconds.

So, bandwidth = $\frac{32*60*10^6}{12}$

So, 160

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This is NPTEL assignment question.

And hamacher also has one question like this in the exercise.

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Could anyone verify this, I think minimum time would have been without considering there is a miss in cache when reads request is served but since there is no info on it how cache would work so we assumed that there is a miss for every request so this is worst case speed system have right?

Answer 1

Few things which are to be noted here are as follows. The memory controller is a part of the “memory system”. The memory system quite obviously also has the memory chip where the data are actually stored. Now the question asks to find the maximum bandwidth of the “memory system”. Now bandwidth of the memory system is the data transfer speed of the memory system, i.e. considering memory system as a black box, how much data can be retrieved from it per unit time.

Now as per the question it takes $1$ cycle to select the first address of the block by the memory controller.

It takes $3$ cycles to read $8$ words from the memory chip to the memory controller. [Note that the memory controller is a part of the memory system, so $8/3$ words/cycle is not the required bandwidth, we need to find data rate for data entering or leaving the memory system!!]

Lastly it takes $8$ cycles to transfer the $8$ words to the data bus.

So in a period of $1+3+8(=12)$ cycles, $8$ words or $32$ bytes of data are retrieved from the memory system. So in a system which issues a series of read request, the maximum bandwidth of the memory system shall occur when there is a miss!! [Had there been no miss, the memory system shall be idle and bandwidth shall be $0$ in that case.] So in a system issuing a series of read requests, in $12$ cycles or $12*\frac{1}{60 *10^6}$ secs we can get max of $32$ bytes of data out of the memory system.

So required bandwidth = $\frac{32}{12*\frac{1}{60 *10^6}}$ bytes/sec = $160 * 10^6$ bytes/sec

Comments

Mind blowing explanation lad.

Answer 2

total number of cycles = 1 + 3 + 8 = 12

total data transferred = 8 words * 4 bytes per word = 32 bytes

frequency of clock = 60 MHz

so bandwidth = total data transferred/total time taken

 = 32  bytes/(12cycles/(60*10^6cycles per sec))

= 160 * 10 ^ 6 bytes/sec

It is maximum in the case when every read request is a cache miss.

Answer 3

$T=1/60\ \mu s\ per\ cycle$

TOTAL no of cycles required to transfer 1 cache block of size 32 Bytes is

= 1+3+1*8

= 12 cycles

TOTAL time taken in case of cache miss =12*1/60 $\mu s$

= 0.2 $\mu s$

Now, Bandwidth = 32/0.2 * $10^6$B per sec

= 160 * $10^6$ B/s

Note here that we are considering the max bandwidth from main memory to cache which happens only when there is a cache miss and not from cache to processor.

Comments

How did you come to the conclusion that we are talking about main memory to cache as it's not explicitly written in the question? The question seems very unclear to me.

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gud question

Answer 4

Cache block = 8 words
Word size = 4 bytes
Cache block size = 32 bytes
Clock = 60 MHz
⇒ T = 1/clock = 1/60×10^6 seconds
Cache miss
= 1 cycle(Address) + 3 cycles (8 words) + 1word/cycle ×8 (transfer)
= 12 cycles
= 12/60×10^6
Total bandwidth = total data/total time = 32 bytes/(12/60×10^6) = 160 × 10^6 bytes/second
Answer: 160

Comments

I am getting answer  as 166 bytes per second. First convert 60 mega Hertz as 1 /(60*10^6). = 16 nsec .To fetch a block from main memory it requires 12 clock cycles

12×16nsec = 192 nsec

In 192 nsec 32 bytes are transferred so in one second 32/(192 ×10^(-9))

166 × 10 ^(6) bytes per second

Is 166 right.?