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A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the starting address of the block, it then takes $3$ cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of $1$ word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of road operations is  ______$\times 10^6$ bytes/sec

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+2
I got 160.

On miss it require total 12 clock cycle.

And 1 clock cycle cost is $\frac{1}{60}$ micro sec. So for 12 clock cycle it would require 0.2 micro second. Which means on 1 miss it require a total of 0.2 micro second in which 32 byte of data can be transmitted. So in 1 sec it can transmit 160×10^6 Byte of data, which is its bandwidth.

Time to transfer a cache block $= 1+3+8 = 12$ cycles.

i.e., $4$ bytes $\times 8 = 32$ bytes in $12$ cycles.

So, memory bandwidth $= \frac{32}{12 \text{ cycle time}} =\frac{32}{12/(60 \times 10^6)}= 160 \times 10^6$ bytes/s
by Veteran (416k points)
selected
0

Sir when block has came into cache

Only one word should be fetched why we are accessing whole block while the address request is of word not block.

1+3+1 = 5 cycles should be delay.

Which gives ans 384.

@Arjun sir plz confirm

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@Arjun Sir I got 160.06 as the answer. Will it be considered as correct. The thing is I did 60MHz =(1/60)*10^6 second which is 0.01666 *10^6 seconds . So the calculation would be 160.06 *10^6 bytes/ second. Will there be a range for this answer.

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Block is the smallest unit of transfer between main memory and cache. Word is between cache and CPU.

Regarding range -- it depends on those making official key. They might give a range.
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here we have to fetch all 8words completely which could be done in 8cycles(total at once),not to considered as single cycle every time.
ans should be 160
by Junior (591 points)
by (221 points)
0
How can you explaine
+1 vote
Yes ans should be 160.
by (37 points)
total number of cycles = 1 + 3 + 8 = 12

total data transferred = 8 words * 4 bytes per word = 32 bytes

frequency of clock = 60 MHz

so bandwidth = total data transferred/total time taken

= 32  bytes/(12cycles/(60*10^6cycles per sec))

= 160 * 10 ^ 6 bytes/sec

It is maximum in the case when every read request is a cache miss.
by Active (2k points)
$T=1/60\ \mu s\ per\ cycle$

TOTAL no of cycles required to transfer 1 cache block of size 32 Bytes is

= 1+3+1*8

= 12 cycles

TOTAL time taken in case of cache miss =12*1/60 $\mu s$

= 0.2 $\mu s$

Now, Bandwidth = 32/0.2 * $10^6$B per sec

= 160 * $10^6$ B/s

Note here that we are considering the max bandwidth from main memory to cache which happens only when there is a cache miss and not from cache to processor.
by Loyal (9.2k points)
Cache block = 8 words

Word size = 4 bytes

Cache block size = 32 bytes

Clock = 60 MHz

⇒ T = 1/clock = 1/60×10^6 seconds

Cache miss

= 1 cycle(Address) + 3 cycles (8 words) + 1word/cycle ×8 (transfer)

= 12 cycles

= 12/60×10^6

Total bandwidth = total data/total time = 32 bytes/(12/60×106) = 160 × 10^6 bytes/second

by (149 points)

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