A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the starting address of the block, it them takes $3$ cycles to fetch all the eight words of the block, and finaly transmits the words of the requested block at the rate of $1$ word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of road operations is ______$\times 10^6$ bytes/sec
Sir when block has came into cache
Only one word should be fetched why we are accessing whole block while the address request is of word not block.
1+3+1 = 5 cycles should be delay.
Which gives ans 384.
@Arjun sir plz confirm
@Arjun Sir I got 160.06 as the answer. Will it be considered as correct. The thing is I did 60MHz =(1/60)*10^6 second which is 0.01666 *10^6 seconds . So the calculation would be 160.06 *10^6 bytes/ second. Will there be a range for this answer.