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63 votes

Assume that in a certain computer, the virtual addresses are $64$ bits long and the physical addresses are $48$ bits long. The memory is word addressible. The page size is $8$ kB and the word size is $4$ bytes. The Translation Look-aside Buffer (TLB) in the address translation path has $128$ valid entries. At most how many distinct virtual addresses can be translated without any TLB miss?

  1. $16 \times 2^{10}$
  2. $256 \times 2^{10}$
  3. $4 \times 2^{20}$
  4. $8 \times 2^{20}$
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Best answer
100 votes
100 votes

TLB Entry: $\begin{array}{|l|l|} \hline  \text{Page Number} & \text{Frame Number} \\ \hline \end{array}$

Memory is $\text{word addressable.}$

  • Word size $=  4 \text{ Bytes} $
  • Page size $ =  8\;\text{KB} = 2^{11}  \text{ words}$
  • Virtual Memory size $= 2^{64} \text{ words}$
  • Number of pages possible $= 2^{53}$
  • Number of bits required for Page number $= 53 \text{ bits}$
  • Number of bits required for Page offset $= 64-53 =11 \text{ bits}$

At a time TLB contains $128=2^{7} $ distinct page numbers.

If a page number is found in TLB then there will be a hit for all the words (Word addresses) of that Page.

$1$ - page hit implies $2^{11}$ distinct virtual address hits.

So $2^{7} $page hit implies $2^7 \ast 2^{11} = 2^8\ast 2^{10} = 256 \ast 2^{10} \text{ virtual  address hits}$

Option B. At most, $256 \ast 2^{10}$  distinct virtual addresses can be translated without any TLB miss.

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30 votes
30 votes
VA = <pageNo, offset>

Here total no of TLB entries is 128 which means 128 Virtual Address to Physical Address translations can be stored. These entries store frame no for the corresponding page no. Assuming we already have 128 distinct valid TLB entries present.

Now 1 page contains #words = Page Size / 1 word = 8 KB/ 4 B = 2K

Now each TLB entry contains 1 frame no  and each page/frame can contain max 2K words.

Thus the TLB can address 128 * 2K or 256 * 1K words without any miss.

Ans B) $256 * 2^{10}$
5 votes
5 votes

TLB that contains page table entries (those are most frequently used) is a hardware device to reduce memory access time. It has 128 entries(pages). 

since the memory is word addressable, means cpu will access 1 word at a time. so we need to find no. of words in 1 page = 4kB/4B = 2^11.

so now 1 page has 2^11 addresses & tlh has 128 pages so total distinct addresses that can be translated with tlb = 2^11 * 128 = 256*2^10.

option B

2 votes
2 votes

Each address corresponds to a word. (Page number + Page offset leads to a word in a page. Same for Frame number + Frame Offset)

TLB has $128=2^7$ valid entries. Each entry leads to a page. Each page has $\frac{8kB}{4B}=2^{11}$ words.

So, for a maximum number of $2^{11}*2^7=2^{18}$ addresses, we can have a hit.

 

Option B

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