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The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

  1. C800 to CFFF
  2. CA00 to CAFF
  3. C800 to C8FF
  4. DA00 to DFFF
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$(A_{15} \:  A_{14} \:  A_{13} \:  A_{12} \:  A_{11} \:  A_{10} \:  A_9 \:  A_ 8 \: A_7 \: A_6 \: A_5 \:  A_4 \: A_3 \: A_2 \: A_1 \: A_0)$

According to question:

$A_{15} = 1, \: A_{14} = 1, \: A_{13} = 0, \:  A_{12} = 0, \: A_{11} = 1$

So the possible range in binary:

$(\bf{1 1 0 0 1}$$ 0 0 0 0 0 0 0 0 0 0 0) \text{ to } (\bf{1 1 0 0 1}$$ 1 1 1 1 1 1 1 1 1 1 1)$

Converting to Hexadecimal:

$(C800) \text{ to } (CFFF)$

Option A.
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The memory system that can be enabled by the chip select signal

$\rightarrow$ From this we can understood that, $CS$ should be $1$.

$\rightarrow$ Note that it is $AND$ gate, $\implies$ all input lines should be $1$.

$\rightarrow$ $A_{15}$.$A_{14}$.$\overline{A_{13}}$.$\overline{A_{12}}$.$A_{11}$ = $1\implies$ $(A_{15} = 1$ and $A_{14} = 1$ and $\overline{A_{13}} = 1$ and $\overline{A_{12}} = 1$ and $A_{11} = 1)$

$\rightarrow$ $\overline{A_{13}} = 1$ $\implies$ ${A_{13}} = 0$

$\rightarrow$ $\overline{A_{12}} = 1$ $\implies {A_{12}} = 0$

$\therefore$ The address denoted by A$_{15}$ to A$_0$ is , (Note A$_{15}$ as MSB and A$_{0}$ as LSB)

 (1100) (1__ __ __) (__ __ __ __ ) ( __ __ __ __ )

$\rightarrow$ For starting address,keep all $\bf{0}$'s in the blanks, and for ending address keep all $\bf{1}$'s in the blanks.

$\rightarrow$ Starting address :- 1100 1$\bf{000}$ $\bf{0000}$ $\bf{0000}$$\implies$(C800)$_H$

$\rightarrow$ Ending address :- 1100 1$\bf{111}$ $\bf{1111}$ $\bf{1111}$$\implies$(CFFF)$_H$

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