It has been given that the CPU's are identical , with only one difference , one has a pipelined architecture , i.e while some unit e.g the decoding is happening , instruction fetch and PC increment unit can be carried out in the same clock cycle(of course with the use of interstage buffer) , and the other CPU has a non-pipelined architecture , i.e no sharing of clock cycles takes place.
We can safely take into assumption that no interstage buffer is being used in the non-pipelined architecture.
Let's say both the CPU's have 5 stage data path , namely $IF , ID , IE, M , WB$.
Let's say each stage takes $x \ clock \ cycles$.
In case of pipelined processor , let the interstage buffer delay = $y \ clock \ cycles$.
Total clock cycles for execution of an instruction in pipelined architecture(T1) = $5x+4y$ clock cycles.
Total clock cycles for execution of an instruction in non-pipelined architecture(T2) = $5x$.
In this scenario , T1>T2.
Now if non-pipelined architecture too had interstage buffers , then total time would've been = $5x+4y$.
In this scenario , T1= T2.
Thus $T1>=T2$ shall be correct.
Pipelining speeds up in long run , for only one instruction it is as good as non-pipelined version.