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When using pipelining can we have an arrangement like this?

I1 F1 D1 E1 M1 W1          
I2   F2 ______ ____ _____ D2 E2 M2 W2  
I3     F3 D3 E3 M3 W3      

Where  I2 has Read after write dependency  on I1 and operand forwarding is not used.

I3 is independent of I1 and I2

F=INSTRUCTION FETCH.

D=DECODING AND READING THE OPERANDS FROM THE REGISTER

E=EXECUTE

M=MEMORY OPERATION

W=WRITE BACK

 

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