I guess it's 7,let's draw the pipelined execution table:-
|
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
$I_{1}$ |
F |
D |
E |
M |
W |
|
|
|
$I_{2}$ |
|
F |
stall |
D |
E |
M |
W |
|
I2 has to wait and postpone it's decoding and operand reading phase till data has been written into R1.The stall has been reduced to 1 due"Operand forwarding" and it uses previously calculated data(or,data after execution phase of the last instruction).So,according to me it's 7.