The delay of NAND and Not gate is 3 and 1ns respectively. And counter is assumed to be 0. If the clock frequency is 500 MHZ,then counter behave as Mod 5 counter Mod 7 counter Mod 6 Counter None

for a synchronous sequential circuit shown below the output Z is zero for initial condition QA QB QC = QA' QB'QC'=000 the minimum number of clock cycle after which the output Z again become zero is________????