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Galvin Edition 9 Exercise 1 Question 24 (Page No. 51)
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Discuss, with examples, how the problem of maintaining coherence of cached data manifests itself in the following processing environments:
a. Single-processor systems
b. Multiprocessor systems
c. Distributed systems
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Galvin Edition 9 Exercise 1 Question 23 (Page No. 51)
Consider an SMP system similar to the one shown in Figure 1.6. Illustrate with an example how data residing in memory could in fact have a different value in each of the local caches.
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Galvin Edition 9 Exercise 1 Question 22 (Page No. 51)
Many SMP(Symmetric Multiprocessing) systems have different levels of caches; one level is local to each processing core, and another level is shared among all processing cores. Why are caching systems designed this way ?
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Galvin Edition 9 Exercise 1 Question 21 (Page No. 51)
Some computer systems do not provide a privileged mode of operation in hardware. Is it possible to construct a secure operating system for these computer systems ? Give arguments both that it is and that it is not possible.
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Galvin Edition 9 Exercise 1 Question 20 (Page No. 51)
Direct memory access is used for high-speed I/O devices in order to avoid increasing the CPU's execution load. a. How does the CPU interface with the device to coordinate the transfer ? b. How does the CPU know when ... Does this process interfere with the execution of the user programs ? If so, describe what forms of interference are caused.
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