Total latch latency

Question

Suppose there is unpipelined processor with a cycle time 30 ns which is evenly divided into 5 pipeline stages. The total latch latency of the pipeline will be _______________ ns.

Comments

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Answer 1

since there are 5 stages in pipelined processor and cycle time is evenly divided into 5 stages

    it implies=>

         30/5 = 6ns of cycle time per stage

so total cycle time in pipelined processor=6+1=7ns

now total latency time= cycle time of pipeline processor * number of stages

                              =7 * 5

                     =35 ns  (Answer)