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How many memory accesses are there in this code?

LOAD R1, a(RO)
in CO and Architecture by Active (4k points) | 72 views

1 Answer

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3 mem refrence is required

 

by Boss (34.4k points)
0

@abhishekmehta4u

Fetching doesnot required memory

Am I right?

0
by default instn are in memory . and fetching mean you go to the memory and take starting address of the program . so we need to visit one mem refrence.
0

@abhishekmehta4u

PD is the execute stage 

right?

what about this stage?

0
Where is the "+" coming from?
0
operand fetch stage
0

@Arjun

sir i am assuming instn is base indexed addresing mode.

 

0
R1 <- M[A+ R0]

Can you give reference for any other interpretation than this?

Then, what is "A"?
0
Why do we need pipeline here?

$LOAD$ $ R1, a(RO)$

here $a(R_{0})$ can be indirect addressing mode too

Am I right?

Then loading from memory requires only $1$ memory which added with register value
0
What is "A"?
0

a is not defined, but it is showing like some memory address

it is like this question of hamacher https://gateoverflow.in/308334/carl-hamacher-machine-instruction-and-programs-chapter-%242%24

 

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