0 votes 0 votes How many memory accesses are there in this code? LOAD R1, a(RO) CO and Architecture effective-memory-access co-and-architecture + – aditi19 asked Apr 1, 2019 aditi19 814 views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes 3 mem refrence is required abhishekmehta4u answered Apr 1, 2019 abhishekmehta4u comment Share Follow See all 10 Comments See all 10 10 Comments reply srestha commented Apr 1, 2019 reply Follow Share @abhishekmehta4u Fetching doesnot required memory Am I right? 0 votes 0 votes abhishekmehta4u commented Apr 1, 2019 reply Follow Share by default instn are in memory . and fetching mean you go to the memory and take starting address of the program . so we need to visit one mem refrence. 0 votes 0 votes srestha commented Apr 1, 2019 reply Follow Share @abhishekmehta4u PD is the execute stage right? what about this stage? 0 votes 0 votes Arjun commented Apr 1, 2019 reply Follow Share Where is the "+" coming from? 0 votes 0 votes srestha commented Apr 1, 2019 reply Follow Share operand fetch stage 0 votes 0 votes abhishekmehta4u commented Apr 1, 2019 reply Follow Share @Arjun sir i am assuming instn is base indexed addresing mode. 0 votes 0 votes Arjun commented Apr 1, 2019 reply Follow Share R1 <- M[A+ R0] Can you give reference for any other interpretation than this? Then, what is "A"? 0 votes 0 votes srestha commented Apr 1, 2019 reply Follow Share Why do we need pipeline here? $LOAD$ $ R1, a(RO)$ here $a(R_{0})$ can be indirect addressing mode too Am I right? Then loading from memory requires only $1$ memory which added with register value 0 votes 0 votes Arjun commented Apr 3, 2019 reply Follow Share What is "A"? 0 votes 0 votes srestha commented Apr 4, 2019 reply Follow Share a is not defined, but it is showing like some memory address it is like this question of hamacher https://gateoverflow.in/308334/carl-hamacher-machine-instruction-and-programs-chapter-%242%24 0 votes 0 votes Please log in or register to add a comment.