The D-type positive edge triggered flip-flop of the figure is modified by including an asynchronous clear input in the circuit. The Asynchronous clear input is connected to the third input in gate 2 and also to the third input in gate 6.
- Draw the logic Diagram of the flipflop, including the asynchronous clear input.
- Analyze the circuit and show that when the synchronous clear input is logic-0, the Q output is cleared to 0 regardless of the values of the other two inputs. D and CP.
- Show that when asynchronous clear input is at logic 1, it has no effect on the normal operation of the circuit.
