Total cache size is 4 blocks.
Memory accesses are as follows: 0 , 11 , 4 , 14 , 9 , 1 , 8 , 0
So, the corresponding block numbers will be: 0, 5, 2, 7, 4, 0, 4, 0 (000, 101, 010, 111, 100, 000, 100, 000)
0, 5, 2, 7 and 4 causes compulsory misses as they are first accesses to blocks.
Next 0 is a capacity miss as after the previous access to 0, we have 4 unique block accesses and we have capacity only for $4-1=3$ more. Being a capacitive miss it cannot be a conflict miss (Conflict miss is a miss which won't happen in a fully associative cache with LRU policy)
Next 4 is a conflict miss due to 0 replacing 4 but not a capacity miss.
Similarly final 0 is also a conflict miss but not capacity miss.
No. of misses = 8
No. of compulsory misses = 5
No. of conflict misses = 2
No. of capacity misses = 1
More Explanation: https://gateoverflow.in/20086/page-replacement