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Yes you are right but only in case the Cache is Physically Addressed.

Cache memory may be Physically Addressed as well as Virtually Addressed.

If Cache is Physically Addressed then TLB will reside between CPU and Cache because CPU does a TLB lookup on every memory operation and the resulting physical address is sent to the cache.

But in case Cache is virtually Addressed then CPU generated addresses i.e. Virtual Address will directly looked up in Cache and In case of cache miss, we need the address translation then only TLB will be accessed.

In multi level Cache organization,TLB may reside even between two cache.

Reference - https://en.wikipedia.org/wiki/Translation_lookaside_buffer and https://en.wikipedia.org/wiki/CPU_cache

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