If a page is not present in the memory, then its corresponding entry in the page table would have the ‘Present’ bit set as 0 to indicate , the page is not present.
Will this entry be considered for caching in TLB?
As I understand from above line in Tanenbaum, The entry should not be present in TLB. Is my understanding right?
I think it depends on implementation. If when the PTE valid bit is set to 0 then of it is in TLB it is deleted, then such entry willn't be there else it will be there.
Can a TLB hit lead to page fault in memory?
Yes. One example is if the memory access is different from the allowed one.
e.g. you want to write to memory that's write protected. A TLB exists, it's a hit and the address is translated. But on access you get a trap, as you're trying to write to memory that's read-only