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Consider a $5$-stage instruction pipeline. The stages and the corresponding stage delays are given below.

$$\begin{array}{|l|l|}\hline \textbf{Instruction}&\textbf{stage delay}\\\hline  \hline \text{Fetch instruction (FI)}&\text{3 ns}\\\hline \hline \text{Decode instruction (DI)}&\text{4 ns}\\\hline \hline \text{Fetch operand (FO)}&\text{7 ns}\\\hline \hline \text{Execute instruction (EI)}&\text{10 ns}\\\hline \hline \text{Write result (WR)}&\text{7 ns}\\\hline \end{array}$$

Assume that there is no delay between two consecutive stages. Consider a processor with a branch prediction mechanism by which it is always able to correctly predict the direction of the branch at the $FI$ stage itself, without executing the branch instruction.A program consisting of a sequence of 10 instructions $I1, I2, . . . , I10$, is executed in the pipeline, where the $5th$ instruction $(I5)$ is the only branch instruction and its branch target is the $8th$ instruction $(I8)$.

  1. Draw the pipeline diagram over time showing how the instructions $I1, I2, . . . , I10$ flow through the pipeline stages in this processor.
  2. Calculate the time $(in\ ns)$ needed to execute the program.
in Operating System by Boss (41.4k points) | 58 views
b- 120 ns
pls, give proper reasoning...

1 Answer

0 votes
120ns is the answer.

total clock cycle =12
by (27 points)

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