ISI2018-PCB-CS8

Question

Consider a $5$-stage instruction pipeline. The stages and the corresponding stage delays are given below.

$$\begin{array}{|l|l|}\hline \textbf{Instruction}&\textbf{Stage delay}\\\hline  \hline \text{Fetch instruction (FI)}&\text{3 ns}\\\hline \hline \text{Decode instruction (DI)}&\text{4 ns}\\\hline \hline \text{Fetch operand (FO)}&\text{7 ns}\\\hline \hline \text{Execute instruction (EI)}&\text{10 ns}\\\hline \hline \text{Write result (WR)}&\text{7 ns}\\\hline \end{array}$$

Assume that there is no delay between two consecutive stages. Consider a processor with a branch prediction mechanism by which it is always able to correctly predict the direction of the branch at the $FI$ stage itself, without executing the branch instruction.A program consisting of a sequence of $10$ instructions $I1, I2, . . . , I10$, is executed in the pipeline, where the $5^{th}$ instruction $(I5)$ is the only branch instruction and its branch target is the $8^{th}$ instruction $(I8)$.

1. Draw the pipeline diagram over time showing how the instructions $I1, I2, . . . , I10$ flow through the pipeline stages in this processor.
2. Calculate the time $\text{(in ns)}$ needed to execute the program.

Comments

b- 120 ns

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pls, give proper reasoning...

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150ns is right answer

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https://gateoverflow.in/217206/isi-mtech-pcb-2018

Answer 1

120ns is the answer.

total clock cycle =12

Comments

Instruction 5 only executes IF state & immediately jumps to Instruction 8, which means at 5th clock cycle only IF of I5 will be executed & from next clock cycle, from 6th Instruction 8 will be executed.

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i think you are wrong...can you please review your solution and provide it with detail

Answer 2

In this pipeline system, no buffer is present, so maximum time to execute the program $10\times 12=120ns.$

$$\small \begin{array}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline
&\bf{t_1}&\bf{t_2}&\bf{t_3}&\bf{t_4}&\bf{t_5}&\bf{t_6}&\bf{t_7}&\bf{t_8}&\bf{t_9}&\bf{t_{10}}&\bf{t_{11}}&\bf{t_{12}}\\
\hline
\textbf{I1}&\text{FI}&\text{DI}&\text{FO}&\text{EI}&\text{WO}\\
\textbf{I2}&&\text{FI}&\text{DI}&\text{FO}&\text{EI}&\text{WO}\\
\textbf{I3}&&&\text{FI}&\text{DI}&\text{FO}&\text{EI}&\text{WO}\\
\textbf{I4}&&&&\text{FI}&\text{DI}&\text{FO}&\text{EI}&\text{WO}\\\textbf{I5}&&&&&\text{FI}&\text{DI}&\text{FO}&\text{EI}&\text{WO}\\
\textbf{I8}&&&&&&\text{FI}&\text{DI}&\text{FO}&\text{EI}&\text{WO}\\
\textbf{I9}&&&&&&&\text{FI}&\text{DI}&\text{FO}&\text{EI}&\text{WO}\\
\textbf{I10}&&&&&&&&\text{FI}&\text{DI}&\text{FO}&\text{EI}&\text{WO}\\

\hline\end{array}$$

for more https://gateoverflow.in/330/gate2013-45

Comments

@srestha answer should be 120 right?

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@s1mple0

then this line “where the 5th instruction (I5) is the only branch instruction and its branch target is the 8th instruction (I8).” only to skip the instruction?

I am not getting actually what this line want to convey?

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@srestha

yes. we need to skip I6,I7