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A $3\times 8$ decoder with $2$ enable inputs is used to  address $8$ block of memory. What will be the size of each memory block when addressed from a $16$ bit bus with $2$ MSB’s used to enable the decoder?
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I have doubt that how these 2 enable inputs are used for $3\times 8$ decoder? Is this the 2 inputs from 3 input ends.
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yes, I havenot got it properly

It is given that decoder is 3x8 with 2 enable inputs. Now, input lines must be split such that two of them act as enable and only 1 act as input line. As shown in below diagram :

Please note here that 1x8 DEMUX requires 3 select lines. Hence we need to use input line as 3rd select line.

Now we have 16 bits address having 2 bits for ENABLE inputs (A,B) and another bit C I will take for Input line.

So overall I am taking first three bits of address as DEMUX select lines so that it activates one of the 8 output lines at a time, which will select one of the 8 RAM blocks.

 A B C

First two bits (AB) of the address will act as enable of decoder (because it is as mentioned in question), third bit C will act as input line, and combination of ABC together will activate the respective output line. A is MSB here and C will be LSB.

Now we have 13 bits that can be the maximum possible address bits which can be used for memory. So size of each memory block will be $2^{13}$ bits or $2^{10}$ Bytes or $1KB$

If you want to calculate the address Range :

Block 1 will get selected when ABC=000 and address range will be from 0000000000000000 to 0001111111111111  $[0000-1FFF]$ in Hex

Block 2 will get selected when ABC=001 and address range will be from 0010000000000000 to 0011111111111111 $[2000-3FFF]$ in Hex

Block 3 will get selected when ABC=010 and address range will be from 0100000000000000 to 0101111111111111 $[4000-5FFF]$ in Hex

And so on.... Hope its correct.

by (337 points)
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input and one select line is same??
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Yes we need to take help of input line for de-multiplexer to work as expected and so that it works on a logic of how to select the required RAM block with a given 16 bit address.

I found no other way to interpret "3×8 decoder with 2 enable inputs" ?
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@APOORV PANSE

decoder always have $N:2^{N}$ input and output line

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In the circuit I made, input lines are 3 only (A,B,C) and output lines are 8. The way I am implementing the internal structure is how the question wants us to make it.

Even though they mentioned "decoder", they wants us to interpret it as a "demux". Please let me know in case you have any other way to solve the question.

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+1 vote