$((XY')' YZ)'$
$= XY' + Y' + Z'$
$= Y'(1+X) + Z'$
$= Y' +Z'$
$= (YZ)'$
$\therefore$ we need only $1$ NAND gate to implement the above circuit.
Also we can make NAND gate using $4$ NOR gates.
So we need $4$ NOR gates to implement the above circuit.
$\therefore$ Option $A$ is the correct answer.