1 votes 1 votes Q.58 Consider 5 stage pipeline which allow all instructions except branch instruction. Program contain 30% conditional instructions out of which 75% are branch instruction. Processor stop fetching the following instruction after the branch instruction untill target address is available. Target address is available at the end of the pipeline stage. All the stages are perfectly balanced with 20 GHz clock time. The processor is running with rate of ____________ (in MIPS). Given answer -> 92 CO and Architecture co-and-architecture pipelining made-easy-test-series + – Akash Kanase asked Dec 19, 2015 • edited Mar 5, 2019 by ajaysoni1924 Akash Kanase 363 views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
