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Q.42

Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied with

A 4 bit data 1011 is applied to the shift register 1. What is the minimum number of clock pulses required to get same input data at output are with same clock?

  • 11
  • 12
  • 13
  • 14

Please answer !

in Digital Logic by Boss (41.9k points)
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1 Answer

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  SISO SIPO PISO
T0 0000 0000 0000
T1 1000 0000 0000
T2 1100 0000 0000
T3 0110 0000 0000
T4 1011 0000 0000
T5 0101 1000 0000
T6 0010 1100 1000
T7 0001 0110 1100
T8 0000 1011 0110
T9 0000 0101 1011
T10 0000 0010 0101
T11 0000 0001 0010
T12 0000 0000 0001
T13 0000 0000 0000

I have used the above approach according to this after 12 clock pulses, 1011 will be at output.

by Active (1.6k points)
0
T0 to T12  are 13 clock cycles and not 12

I got the same chart and my ans is 13 how are you getting 12?
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