MadeEasy Test Series: CO & Architecture - Addressing Modes

The Data transfer instruction size is $64-bit$ ALU, ALU operation instruction size is $32-bit$ and branch instruction size is $16-bit$. Assume program has been loaded in ...

Learner_jai

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Learner_jai asked Dec 27, 2018

CO and Architecture
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Rishabh Gupta 2 asked Jan 30, 2018

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MadeEasy Test Series: CO & Architecture - Addressing Modes
A computer has 256 KB, 8 way set associative write back data cache with block size 16 bytes. The processor send 36 bit addresses to the cache controller. Each tag directory entry contains, in addition to tag address, 1 valid bit and 1 matching bit. The size of ... above till here: TAG Size = $23\ bits * 2^{14}$ = $3\ bytes * 2^{14}$ = 48 KB

A computer has 256 KB, 8 way set associative write back data cache with block size 16 bytes. The processor send 36 bit addresses to the cache controller. Each tag directo...

Rishabh Gupta 2

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Rishabh Gupta 2 asked Jan 30, 2018

CO and Architecture
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cache-memory
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addressing-modes

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Hradesh patel asked Nov 27, 2016

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MadeEasy Test Series: CO & Architecture - Addressing Modes
Q. Consider an instruction of indirect addressing mode. what is the number of memory refrence by the processor when instruction is a computation that require a single operand and when it is a branch Instruction respectivily ?/ Option A) 2 ,2 B) 3,3 C)3,2 D) 2,3

Q. Consider an instruction of indirect addressing mode. what is the number of memory refrence by the processor when instruction is a computation that require a single ...

Hradesh patel

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Hradesh patel asked Nov 27, 2016

CO and Architecture
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vaishali jhalani asked Nov 23, 2016

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MadeEasy Test Series: CO & Architecture - Addressing Modes
Here we will consider memory as word addressable or byte addressable?

Here we will consider memory as word addressable or byte addressable?

vaishali jhalani

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vaishali jhalani asked Nov 23, 2016

CO and Architecture
made-easy-test-series
co-and-architecture
addressing-modes

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