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+9 votes
A priority encoder accepts three input signals $(A,B$ and $C)$ and produce a two-bit output $(X_{1},X_{0})$ corresponding to the highest priority active input signal. Assume $A$ has the highest priority followed by $B$ and $C$  has the lowest priority. If none of the inputs are active the output should be $00$. Design the priority encoder using $4:1$ multiplexers as the main components.
asked in Digital Logic by Veteran (406k points)
edited by | 1.2k views

4 Answers

+8 votes

We can implement the priority encoder using two $4:1$. Multiplexers as main components and $1$ NOT gate and $1$ OR gate
Using following truth table (Priority encoder with highest priority to $A$)

answered by Boss (11.3k points)
edited by
Can you please explain logic behind second mux? I'm getting the answer here :
i know the priority encoders but not able to understand this above concept plz clear me????
+3 votes

we know the truth table of priority encoder .

now we have a multiplexer. we need to do selection in a abnormal way. means we have to play with select lines . and we have 2 output from the above function. relize them and then give input to the select line of muxs.

y1= i3+i2

y0=i3+ i2' i1

now make y1 as s1 select line .and y0 as s0.

answered by Boss (15.9k points)
I have understood that here we have made selection i/p(s0 and s1) a bit complex in order to select any of the (x3,x2,or x1). But this encoder o/p should be 2 bits. How are we acheiving that thing?
0 votes

$X_0 = \bar{A} \bar{B} C + A$

$X_1 = \bar{A} B  + A$


answered by Boss (34.5k points)
0 votes


Suggestions are welcome.

answered by (33 points)

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