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The parallel bus arbitration technique uses an external priority encoder and a decoder. Suppose, a parallel arbiter has $5$ bus arbiters. What will be the size of priority encoder and decoder respectively?

- $4 \times 2 , \: 2 \times 4$
- $2 \times 4 , \: 4 \times 2$
- $3 \times 8 , \: 8 \times 3$
- $8 \times 3 , \: 3 \times 8$

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Arbiters are electronic devices that allocate access to shared resources.

**Example:**

A bus arbiter is a device used in a multi-master bus system to decide which bus master will be allowed to control the bus for each bus cycle.

Since, it is given that the parallel arbiter has 5 bus arbiters. Hence, number of bits required to provide 5 bus arbiters are 3 bits (Since, $2^3$ = $8$).

Now encoder is a type of combinational circuit which consist of $2^n$ input lines and $n$ output lines i.e., $2^n X n$ encoder. Now, $n$ = $3$ bits. Therefore, size of encoder is $8 $$X$$ 3$. Similarly decoder is a combinational circuit which consist of $n$-input lines and $2^n$ output lines, i.e., $n$$ X $$ 2^n$ decoder. So size of decoder is $3$ $X$ $8$.

Sources:https://en.wikipedia.org/wiki/Arbiter_(electronics)

https://en.wikipedia.org/wiki/Priority_encoder

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