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Consider a 5 stage pipeline with IF, ID, EX, MEM and WB latencies 8, 6, 4, 6 and 4 respectively (in ns). If IF stage is made 50% faster, the percentage it will improve the performance CPU is __________.

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In case of pipeline we have to consider maximum stage delay as uniform delay so in normal case time taken to execute an instruction will be '8ns' as it is highest time taken by IF.

Now as per question IF is becoming 50% faster so new delay for IF stage will be '4ns'. So average time taken by an instruction in second case is max(4,6,4,6,4). which is '6ns'

%performance increased = (8-6/8)*100 = 25%

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