17.3k views

Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is $90$%, and the page fault rate is one in every $10,000$ instructions. What is the effective average instruction execution time?

1. $645$ $nanoseconds$
2. $1050$ $nanoseconds$
3. $1215$ $nanoseconds$
4. $1230$ $nanoseconds$
edited | 17.3k views
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+5
indeed a nice question
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@Arjun sir, Is it possible that for a memory address translation there can be more than one page fault(only for more than one page table)?

as we know page fault is accessing a page that is marked invalid in page table.and suppose there are two page tables and when we try to access page of $PT1$ which is marked invalid and after restoring this page there is again a page fault for $PT2$. Is it possible?
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I think access will be like this

Find page in Page Table 1 , if not found , then search it in Page Table2, if not found then only bought it from main memory
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but @srestha if a page is not present in page table $1$, then How will you know which page to acess at inner level bcz from only outer level pages will have entries for those pages.OR it is possible that those page which have entries at outer level page may not be present at inner levels?

But I have one doubt here --if we have page fault at level-1 then what is the techniqe for storing the pages.

we store only that page or along with it we also restore all those page to which this outer level page is referring to.If it is latter case then only at level-1 can cause page fault and subsequent access to page tables can not lead to page fault otherwise we can get multiple level of page faults for  the same address translation.
+3
Let p be the probability of a page fault (0 s p 5 1). We would expect p to
be close to zero—that is, we would expect to have only a few page faults. The
effective access time is then
effective access time = (1 - p) x ma + p x page fault time.
To compute the effective access time, we must know how much time is
needed to service a page fault. A page fault causes the following sequence to
occur:
1. Trap to the operating system.
2. Save the user registers and process state.
3. Determine that the interrupt was a page fault. '
4. Check that the page reference was legal and determine the location of the
page on the disk.
5. Issue a read from the disk to a free frame:
a. Wait in a queue for this device until the read request is serviced.
b. Wait for the device seek and /or latency time.
c. Begin the transfer of the page to a free frame.
6. While waiting, allocate the CPU to some other user (CPU scheduling,
optional).
7. Receive an interrupt from the disk I/O subsystem (I/O completed).
8. Save the registers and process state for the other user (if step 6 is executed).
9. Determine that the interrupt was from the disk.
10. Correct the page table and other tables to show that the desired page is
now in memory.
11. Wait for the CPU to be allocated to this process again.
12. Restore the user registers, process state, and new page table, and then
resume the interrupted instruction.

for an instruction probability of having page fault = 1/10000
Hence, probability of having not a page fault = 9999/10000

If TLB hit occurs then memory Access time = 150 +150 = 300(two operand are there) and
if TLB miss occurs then Memory Access Time = Access Page Table1 + Page table2 + Two memory Access =150 + 150 + 150 + 150 = 600

Hit ratio of TLB = 90 %

Memory Access Time = 9999/10000 ( 0.90*300 + 0.10*600 ) + 1/10000( 8000000 + .90*300 + .10*600 )
= 329.967 + 800.033
= 1130 ns

Total Time of execution is = CPU Time + Memory Access Time
Total Time of execution is = 100 ns + 1130 ns = 1230ns
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second method

Average Instruction execution time

= Average CPU execution time + Average time for getting data(instruction operands from memory for each instruction)

=   Average CPU execution time
+ Average address translation time for each instruction
+ Average memory fetch time for each instruction
+ Average page fault time for each instruction

= $100+2\Big(0.9 (0) + 0.1 (2 \times 150)\Big) + 2\times 150 + \dfrac{1}{10000} \times 8 \times 10^6$

(Page Fault Rate per 10,000 instruction is directly given in question.Two memory accesses per instruction and  hence we need 2 $\times$ address translation time for average instruction execution time)

[ TLB access time assumed as 0 and 2 page tables need to be accessed in case of TLB miss as the   system uses two-level paging ]

= $100 + 60 + 300 + 800$

= $1260 ns$
edited
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1260 does not option even specified...
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sir i hav e a doubt.. why didn't you multiply 800 with 2? that also part of accessing the byte from memory right?
–2
The solution is not correct because milliseconds have been taken as microseconds.

The correct answer is 2060 nanoseconds.
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@ arjun sir,

If miss in TLB then PA should be obtained from MM from page table.

If requested Page table itself not in MM , Are we considering probability for its page fault also ??
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Will a page table access ever cause page fault? If so what happens after that?

Anyway for this question how and when page fault happens is irrelevant as page fault rate per instruction is given directly.
+1

Will a page table access ever cause page fault if so what happens after that?

@  Sir ...lets say in outer level page table some entry selected and for that entry referred  page table of next level is not in memory then it is loaded in memory and original access restarted again..

correct me if am wrong sir

+2
Never happens. A page table is always in main memory and never swapped out.
0

A page table is always in main memory and never swapped out.

Means while loading new process ..ALL required page tables in all levels are loaded..so page fault happens only for pages corresponding to process and identified by valid bit in Page table..

0
Yes. There is no OS mechanism to handle nested Page Faults.
0
@arjun since it is 2 level paging then why you didn't multiply it with 3 because it'll take 3 memory readings??

(gate 2004 qus)

EAIET=[CPU execution time]+(TLB Hit*2*Memory access time +TLB miss ratio(page table access time+2*memory access time ))+{page fault probability*page fault service time}
That is 100ns+(0.9*2*150+0.1(150+150+2*150))+800ns.....[800ns herecomes from 0.0001*8*10^6]

=100ns+2*(135+30)ns+800ns
=100ns+2*165ns+800ns
=1230ns

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0.1(150+150+2*150) can u please explain why did you do 150 +150  why is it not just 150
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this part 0.1(150+150+2*150) is not correct when there is a  miss in the TLB then both operands need 2*(150+150)ns time for address translation. and further 2*150ns for actual operands fetch from the memory.

I think this problem has two parts---

1st:- We have to calculate Instruction execution time when Instruction is in Memory.

Execution Time in this case is---

TLB hit(time to execute instruction)+TLB miss(PageTable access + time to execute instruction)

=TLB hit(time to execute instruction)+TLB miss(2*MemoryAccessTime + time to execute instruction)

=TLB hit(CPU time+2*MemoryAccessTime)+TLB miss(2*MemoryAccessTime + (CPU time+2*MemoryAccessTime))

=0.9(400)+0.1(700)

=430 ns

2nd-      Now we also have to include the fact that Instruction may not be in Mainmemory.Then we have to service page fault first             then we execute instruction like above case

So overall effective average instruction execution time would be

=P*(PageFaultServiceTime+InstructionExceTime when in memory)+(1-P)(InstructionExceTime when in memory)

=(1/10000)(8*106+430)+(9999/10000)(430)=1230ns

Please let me knw if there is any issue.

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In second case, why are you not taking the time for address translation?
+1

2nd case is not about address translation.It is about whether instruction is in mainmemory or not.depending on that we have two cases where you see we have InstructionExceTime when in memory which include full instruction execution along with translation(as calculated in case 1)

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0
should not we consider page fault when there is tlb miss why we are considering it to be separate
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chk once more

here page fault is calculated when tlb miss

but thing I notice, it is only calculating when the instruction not in main memory.rt?
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yes page fault will be calculated when instruction will not be in main memory instead of tlb miss. That's why page fault will be with respect to instruction not with respect to memory access
0

=TLB hit(CPU time+2*MemoryAccessTime)+TLB miss(2*MemoryAccessTime + (CPU time+2*MemoryAccessTime))

When a  mis occur then we access two page tables,after that we got physical address,now we should do one more memory reference to read that memory and then we should add + (CPU time+2*MemoryAccessTime))

Can some one clarify on this?

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this answer is not correct. Chk selected ans

Average instruction execution time $= (100+0.9(2*150)+0.1(4*150)+\frac{8*10^{6}}{10^{4}})$ns

$\Rightarrow 1230$ns.

Explainations -

• $2$ memory accesses if page is found in TLB.
• $4$ memory accesses if page is not found in TLB. Additional $2$ memory accesses just because of 2 level page. 2 Memory accesses for 2 page tables would be there on TLB miss.

edited
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4 memory accesses needs for page table(2 level paging * 2 memory access = 4 ) overhead. But 2 memory accesses needs for fetching actual data (what we want) hence it should be 6*150 instead of 4*150.

I think here we are overcomplicating things and question is simple but we need to understand it carefully.

page fault rate is one in every 10,000 instructions.

Page fault service time=8ms.

So, on an average time lost due to page fault per instruction=$\frac{8ms}{10000}=800ns$

Now, to this compute Memory access time using TLB.

$EMAT=0.9(150)+0.1(3*150)=180ns$

Since, 2 Memory References are made, Hence total time=$360ns$

To this, $100ns$ of cpu time.

effective average instruction execution time=$800+360+100=1260ns$

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I understood. Thanks
0
why time lost due to page fault is not included in multiplication of 2 i.e memory references. is time lost due to page fault is independent of no of memory accesses made. Help me in this regard....
0
See here it is given that page fault rate is 1 out of every 10000 instructions. So, Average instruction execution time must be atleast 800ns due to page fault.

So, I think in the final answer,it must be atleast this time-1260ns is average instruction execution time.
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I think page fault is included once because if it's a page fault than it will be brought into main memory, Now 2nd time it will be in main memory only.

Given  -
memory access time (MA)= 150ns
TLB HIT Rate (ht) = 90%
No. Of Levels in paging scheme (k) = 2
Page Fault Service Time (Pf) = 8 milli sec
Page Fault Rate (Pr)= 1/10000

TLB search time= negligible = 0

page fault service time when pagefault  Pf*Pr = 800ns

Instruction Access time (IAT)= 100ns +2*(MA) = 400ns

(hierarchical way )

EAIT = TLB search time  + (TLB MISS * 2 level memory access time) + (page fault service time when pagefault) + Instruction Access time

EAIT= t + (1 - ht) (k*MA) + IAT + (Pr*Pf)
= 0 + (1-0.9)(2*150) + 400 + (800)

= 0 + (0.1)(2*150) + 400 + (800) = 30 + 400 + 800

= 1230 ns

edited
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where have u taken tlb hit?
0

TLB search time is time when page is found in Tlb

+1 vote

T(memory access avg) = .90(150) + .1(150+150+150) = 180 (150- level1, 150-level2 and 150-memory)
T effective = 100+ 2* 180 + 1/10000* 8* 10^6 = 1260.

+1 vote
EAIT = CPU time + 2*(EMAT)

EMAT= (VA addr to PA addr) + (Access the byte from PA)

= TLB access time + (1-TLB hit rate)(2*memory access time) + memory access time + (page fault rate * page servicing time)

= 0 + 0.1(2*150) + 150 + (1/1000)(8 msec)

= ( 30+150+800 ) n sec

= 980 nsec

EAIT = 100 + 2(980)

+4

A/Q:
PAGE FAULT IS OCCURRING ON THE BASIS OF INSTRUCTIONS AND NOT ON THE BASIS OF MEMORY ACCESS.
[the page fault rate is one in every 10,000 instructions.]

[BRIEF INTERPRETATION]

WE NEED TWO MEMORY ACCESS TO FETCH AN INSTRUCTION BUT FOR THE SECOND MEMORY ACCESS PAGE FAULT WILL NOT HAPPEN.

DETAILED EXPLANATION AND INTERPRETATION OF THE PROBLEM:

Remember, the time that we are calculating is "per instruction" or for One single instruction.
Page fault means the process page that CPU wants to access is not present in the main memory and thus needs to be copied into main memory from SECONDARY MEMORY.
Now, when the memory was accessed for the first time, [A/Q:  An average instruction takes 100 nanoseconds of CPU time, and two memory accesses.] at that time only Page fault was resolved and the required instruction was brought in the main memory. So, even if we need two memory access for one instruction, the page fault service needs to be included ONLY ONCE as for the second memory access the same instruction is being accessed which is deemed to be present in the memory on second access.
You have taken the Page fault service time twice. It needs a correction, So subtract 800 from your answer to get 2060-800= 1260.

–1
i dont agree.
+1 vote

Overview:

Main Memory Access Time with page fault: =  Disk Access Time due to Page Fault + Main Memory Access Time without page Fault

= $\Big( \dfrac{1}{10000} \times (8 \times 10^6)\Big )+ \Big( (1- \dfrac{1}{10000}) \times 2 \times 150 )$

= $800 + 299.97$

= $1099.97$

MM Access Time without pagefault = 2 * 150 =300 (Because Mentioned An average instruction takes 2 memory accesses)

Average Instruction Execution Time =  $Avg. CPU Execution Time + \Big((TLB Hit \times MainMemoryAccessTimeWithoutPageFault) + (TLB Miss \times (2 level Page TableAccessTime + MainMemoryAccessTimeWithPageFault)) \Big)$

= $100 + \Big( (0.9 \times 300) + 0.1 ((2 \times 150) + 1099.97)\Big)$

= $509.997 ns \equiv 510ns$

edited

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