1 votes 1 votes Digital Logic digital-logic + – Payal Rastogi asked Dec 25, 2015 Payal Rastogi 5.8k views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
1 votes 1 votes option (a) is correct because using shift register using D-flip flop we can delay serial input signal to appear at serial output by keeping clock at low level for some finite amount of time. Shashank Kumar answered Dec 28, 2015 Shashank Kumar comment Share Follow See 1 comment See all 1 1 comment reply Praveen Saini commented Dec 28, 2015 reply Follow Share I think it is not bcoz we keep the clock at low level for finite amount of time. It should be delayed by n clock pulse if n bit SISO shift register is used. Yes SISO should be correct. Btw I am not sure. 0 votes 0 votes Please log in or register to add a comment.