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Suppose that a machine has $48-bit$ virtual addresses and $32-bit$ physical addresses.

  1. If pages are $4\: KB$, how many entries are in the page table if it has only a single level? Explain.
  2. Suppose this same system has a $TLB$ (Translation Lookaside Buffer) with $32$ entries. Furthermore, suppose that a program contains instructions that fit into one page and it sequentially reads long integer elements from an array that spans thousands of pages. How effective will the $TLB$ be for this case?
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Part a /

virtual address size is 48 bits and 4KB page size is used so we get an offset of 12 bits.

48 – 12= 36 bits remain for page address means there are 2^36 pages

Physical address size is 32 bits and offset is 12 bit hence frame address contain 20 bits or 2.5 byte (some may take 3 byte for byte addressable)

dividing a 4KB page in 2.5 byte entries we get total 1,638.4 or 1638 entries

Part b /

out of 32 entries 1 entry is reserved for page containing program 

page size is 4KB which contain 512 long integer of 8 bytes 

for first access there will be miss and other 511 times there will be hit so 

hit ratio 511/512 = 0.998

 

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