# Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 16 (Page No. 255)

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You are given the following data about a virtual memory system:

1. The $TLB$ can hold $1024$ entries and can be accessed in $1$ clock cycle $(1\: nsec).$
2. A page table entry can be found in $100$ clock cycles or $100\: nsec.$
3. The average page replacement time is $6\: msec.$

If page references are handled by the $TLB\:\: 99\%$ of the time, and only $0.01\%$ lead to a page fault, what is the effective address-translation time?

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