You are given the following data about a virtual memory system:
- The $TLB$ can hold $1024$ entries and can be accessed in $1$ clock cycle $(1\: nsec).$
- A page table entry can be found in $100$ clock cycles or $100\: nsec.$
- The average page replacement time is $6\: msec.$
If page references are handled by the $TLB\:\: 99\%$ of the time, and only $0.01\%$ lead to a page fault, what is the effective address-translation time?