# Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 18 (Page No. 256)

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Section $3.3.4$ states that the Pentium Pro extended each entry in the page table hierarchy to $64$ bits but still could only address only $4\: GB$ of memory. Explain how this statement can be true when page table entries have $64$ bits.

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A machine has $48-bit$ virtual addresses and $32-bit$ physical addresses. Pages are $8\: KB.$ How many entries are needed for a single-level linear page table?
A computer has $32-bit$ virtual addresses and $4-KB$ pages. The program and data together fit in the lowest page $(0–4095)$ The stack fits in the highest page. How many entries are needed in the page table if traditional (one-level) paging is used? How many page table entries are needed for two-level paging, with $10$ bits in each part?
Suppose that a machine has $438-bit$ virtual addresses and $32-bit$ physical addresses. What is the main advantage of a multilevel page table over a single-level one? With a two-level page table, $16-KB$ pages, and $4-byte$ entries, how many bits should be allocated for the top-level page table field and how many for the next level page table field? Explain.
Suppose that a machine has $48-bit$ virtual addresses and $32-bit$ physical addresses. If pages are $4\: KB$, how many entries are in the page table if it has only a single level? Explain. Suppose this same system has a $TLB$ (Translation Lookaside Buffer ... and it sequentially reads long integer elements from an array that spans thousands of pages. How effective will the $TLB$ be for this case?