# Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 23 (Page No. 256)

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How can the associative memory device needed for a $TLB$ be implemented in hardware, and what are the implications of such a design for expandability?

## Related questions

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A computer whose processes have $1024$ pages in their address spaces keeps its page tables in memory. The overhead required for reading a word from the page table is $5\: nsec.$ To reduce this overhead, the computer has a $TLB,$ which holds $32$ (virtual page, physical page frame) pairs, and can do a lookup in $1\: nsec.$ What hit rate is needed to reduce the mean overhead to $2\: nsec?$
Write a program that can be used to compare the effectiveness of adding a tag field to $TLB$ entries when control is toggled between two programs. The tag field is used to effectively label each entry with the process id. Note that a nontagged $TLB$ can be ... your simulation behaves as expected for a simple (but nontrivial) input example. Plot the number of $TLB$ updates per $1000$ references.
Consider the following C program: int X[N]; int step = M; /* M is some predefined constant */ for (int i = 0; i < N; i += step) X[i] = X[i] + 1; If this program is run on a machine with a $4-KB$ page size and $64$-entry $TLB,$ what values ... $TLB$ miss for every execution of the inner loop? Would your answer in part $(a)$ be different if the loop were repeated many times? Explain.