Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 1 (Page No. 429)

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 6 (Page No. 429 - 430)
Suppose that a system uses DMA for data transfer from disk controller to main memory. Further assume that it takes $t_{1}\: nsec$ on average to acquire the bus and $t_{2}\:nsec$ to transfer one word ... acquiring the bus to send one word and acknowledging a transfer also requires acquiring the bus to send one word.

Suppose that a system uses DMA for data transfer from disk controller to main memory. Further assume that it takes $t_{1}\: nsec$ on average to acquire the bus and $t_{2}...

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 5 (Page No. 429)
A DMA controller has five channels. The controller is capable of requesting a $32$-bit word every $40\: nsec.$ A response takes equally long. How fast does the bus have to be to avoid being a bottleneck?

A DMA controller has five channels. The controller is capable of requesting a $32$-bit word every $40\: nsec.$ A response takes equally long. How fast does the bus have t...

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 4 (Page No. 429)
Explain the tradeoffs between precise and imprecise interrupts on a superscalar machine.

Explain the tradeoffs between precise and imprecise interrupts on a superscalar machine.

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 3 (Page No. 429)
Figure $5-3(b)$ shows one way of having memory-mapped I/O even in the presence of separate buses for memory and I/O devices, namely, to first try the memory bus and if that fails try the I/O bus. A clever computer ... idea: try both in parallel, to speed up the process of accessing I/O devices. What do you think of this idea?

Figure $5-3(b)$ shows one way of having memory-mapped I/O even in the presence of separate buses for memory and I/O devices, namely, to first try the memory bus and if th...

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 1 (Page No. 429)

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