ROM - Timing Diagram

Question

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Where did you get this qstn?

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gateforum series.

Answer 1

Ans : 1000

Explanation: Initially input to register A = Bus content at time t1 = 0110 .

After rising edge of clock t1,output of register A = 0110.Hence input of ROM =  0110.Now since enable E = 1,so ROM is enabled and output of ROM  = data present in ROM at address 0110 i.e DATA[6] = 1010 (from the table given).

Hence now BUS content will be  = 1010.

Next after rising edge of t2, this input 1010 will appear as output of register A.Hence it will become input for ROM.

Again since E = 1,output of ROM =  data at 1010 =  data at address at 10 = data[10] = 1000

Hence content of BUS after t2 = 1000.