Correct me if I am wrong.

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+17 votes

A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be:

- 1, 1, 0
- 1, 0, 0
- 0, 1, 0
- 1, 0, 1

0

I am not clear for the use of carry and overflow bit. What i know is that carry flag is generated in unsigned arithmetic and overflow for unsigned. So answer should be c) according to me.

Correct me if I am wrong.

Correct me if I am wrong.

0

No ,overflow flag will be 0 bcoz it is set only if two similar signed nos result in a no with sign opposite to those of operands.

But I have a doubt regarding carry flag. It is set only for unsigned nos I guess.

But I have a doubt regarding carry flag. It is set only for unsigned nos I guess.

+2

Answer is (B).

**$Remarks:$
1.** If there is a carry in MSB and there is a carry out of MSB then there is no overflow as no overflow happening in this question.

for example in this question cn⊕cn-1 = 1, using this logic overflow should occur but both the numbers are of different sign so overflow can't occur, so this logic cn⊕cn-1 = 1(overflow) failed.

+25 votes

Best answer

+4

the overflow flag is usually generated by an exclusive or of the internal carry into and out of the sign bit

0

@Mithilesh Consider the normal meaning of carry as in mathematics. Now, overflow bit is set when carry happens for signed numbers. For unsigned numbers carry bit is set. There is no meaning for carry bit for signed numbers and for overflow bit for unsigned numbers.

In the given question we don't know if the numbers are signed/unsigned. But does it make a difference?

In the given question we don't know if the numbers are signed/unsigned. But does it make a difference?

+3 votes

1 1

01001101

+11101001

-----------------

1 00110110

carry flag=1 (extra bit out of msb)

overflow flag=0 (since both in carry out carry =1 and it is addition of -ve and +ve number so overflow should be equals to 0)

(overflow bit =0 if both in carry out carry =0 or1 / addition of -ve and +ve number

& overflow bit =1 if either one of them is 1 and other is 0)

Sign bit =0 (since msb bit is 0)

therefore option B.

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