edited by
14,192 views
30 votes
30 votes

A processor that has the carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two $2's$ complement numbers $01001101$ and $11101001$. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be:

  1. $1, 1, 0$
  2. $1, 0, 0$
  3. $0, 1, 0$
  4. $1, 0, 1$
edited by

3 Answers

Best answer
42 votes
42 votes

Answer: B

   $01001101$

$+ 11101001$

-----------------

 $100110110$

Carry $= 1$

Overflow = $0$ (In $2's$ complement addition Overflow happens only when: Sign bit of two input numbers is $0$, and the result has sign bit $1$ OR Sign bit of two input numbers is $1$, and the result has sign bit $0$.)

Sign bit = $0$.

edited by
12 votes
12 votes

 1  1

     01001101

   +11101001

  -----------------

 1 00110110

carry flag=1        (extra bit out of msb)

overflow flag=0 (since both in carry out carry =1 and it is addition of -ve and +ve number so                                     overflow should be equals to 0) 

                        (overflow bit =0 if both in carry out carry =0 or1 / addition of -ve and +ve number

                          & overflow bit =1 if either one of them is 1 and other is 0)

Sign bit =0  (since msb bit is 0)

therefore option B.

3 votes
3 votes

        Cout = 1 (Carry)

       Cin = 1

   1

   1

                A

          0

  1

   0

   0

   1

   1

   0

   1

               B

          1

  1 

   1

   0

   1

   0

   0

   1

          Result

          0 (Sign Flag)

  0

   1

   1

   0

   1

   1

   0

Carry Flag = 1

Overflow Flag = Cin XOR Cout = 1 XOR 1 = 0

Sign Flag = 0

Hence correct option - B

Answer:

Related questions

29 votes
29 votes
1 answer
1
30 votes
30 votes
2 answers
4
Ishrat Jahan asked Oct 27, 2014
9,138 views
What Boolean function does the circuit below realize?$xz + \bar{x}\bar{z}$$x\bar{z} + \bar{x}{z}$$\bar{x}\bar{y} + {y}{z}$$xy + \bar{y}\bar{z}$