1 votes 1 votes a) A = 0, 1, 0, 0, B = 1, 0, 1, 1 b) A = 1, 0, 1, 1, B = 0, 1, 0, 0 c) A = 1, 1, 0, 0, B = 1, 1, 0, 0 d) A = 0, 1, 0, 0, B = 0, 1, 0, 0 I thought it would be (c) as previous states should persist for 1st clock. But answer given is (a). Can somebody please explain?? Digital Logic digital-logic flip-flop clock-frequency + – Tushar Shinde asked Dec 30, 2015 • retagged Aug 5, 2017 by Arjun Tushar Shinde 834 views answer comment Share Follow See all 4 Comments See all 4 4 Comments reply अनुराग पाण्डेय commented Dec 30, 2015 reply Follow Share I guess some triggering information should be given in the question. Considering level triggered circuit, insignificant processing delay at gates, and only one transition per gate per second. I got a). 0 votes 0 votes Tushar Shinde commented Dec 30, 2015 reply Follow Share Ok. got it thanks. Actually I was trying to map given inputs with some edge triggered clock (so, was trying to maintain previous states). But, it turns out to be just a plain simple question. Thanx Anurag and Japurva :) 0 votes 0 votes Tendua commented Jan 9, 2016 reply Follow Share @anurag , i think this will be gud , the clock specifies that before counting the circuit was at 0 0 . so we can consider that it will be 1 1 at clock zero .and after that . A = (present value of x * previous stage of B) ' B= ( previous stage of a * current stage of y) ' so it will come right from starting . 0 votes 0 votes अनुराग पाण्डेय commented Jan 9, 2016 reply Follow Share I wasn't sure that whether we are allowed to use the values of $X$ and $Y$ before the $1$st second (starting point of observation), so I put a don't care for $A$ there. 0 votes 0 votes Please log in or register to add a comment.
Best answer 3 votes 3 votes So value of A,B at timing 1,3,5,8 is A:-0,1,0,0 B:-1,0,1,1 So option A is right japurva1 answered Dec 30, 2015 • selected Dec 30, 2015 by Tushar Shinde japurva1 comment Share Follow See all 6 Comments See all 6 6 Comments reply Show 3 previous comments Tendua commented Jan 9, 2016 reply Follow Share see . what i think we have not assumed it its given see the timing diagram . before applying clock the value of x and y are 0 and 0 . so what will be A . a will be one and the b will also be 1 . initially it would have taken 2 cycles. but i am taking it has stabilised as we don't know the circuit started just before it was given. i am taking it was started a lot before and form then on the value are zero , or constant input were there, 0 votes 0 votes Prasanna commented Jan 9, 2016 reply Follow Share confused again 0 votes 0 votes Tushar Shinde commented Jan 9, 2016 reply Follow Share Do not get confused, it is not specified that it will change on edge. So, you are free to assume dat it can work on level triggered clock. So, if first approach didnt work, try this. 0 votes 0 votes Please log in or register to add a comment.