Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Q&A
Questions
Unanswered
Tags
Subjects
Users
Ask
Previous Years
Blogs
New Blog
Exams
Dark Mode
NIELIT 2017 DEC Scientist B - Section B: 49
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
retagged
Oct 21, 2020
by
Krithiga2101
1,099
views
0
votes
0
votes
Which of the following is
false
?
Interrupts which are initiated by an instruction are software interrupts
When a subroutine is called, the address of the instruction following the CALL instruction is stored in the stack pointer
A micro program which is written as $0$’s and $1$’s is a binary micro program
None of the options
nielit2017dec-scientistb
co-and-architecture
interrupts
instruction-format
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
retagged
Oct 21, 2020
by
Krithiga2101
by
Lakshman Patel RJIT
1.1k
views
answer
comment
Follow
share this
share
3 Comments
by
Ashwin Kulkarni
commented
Dec 18, 2017
reply
Follow
share this
Nothing is false here!
option D
2
2
by
habedo007
commented
Apr 11, 2020
reply
Follow
share this
In option (B), the line "address of the instruction following the CALL..." will mean the instruction which will be executed after the subroutine right? won't it be stored in PC?
1
1
by
sachin486
commented
Aug 18, 2020
reply
Follow
share this
yeah i think so
0
0
Please
log in
or
register
to add a comment.
Please
log in
or
register
to answer this question.
1
Answer
0
votes
0
votes
All are true hence ans D
anurag sharma
answered
Aug 19, 2020
by
anurag sharma
comment
Follow
share this
0 Comments
Please
log in
or
register
to add a comment.
Answer:
D
← Previous
Next →
← Previous in category
Next in category →
Related questions
3
votes
3
votes
5
answers
1
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
1,939
views
NIELIT 2017 DEC Scientist B - Section B: 6
A stack organized computer has which of the following instructions? zero-address one-address two-address three-address
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
by
Lakshman Patel RJIT
1.9k
views
nielit2017dec-scientistb
co-and-architecture
instruction-format
0
votes
0
votes
3
answers
2
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
3,697
views
NIELIT 2017 DEC Scientist B - Section B: 40
Which of the following is/are not features of RISC processor? Large number of addressing modes. Uniform instruction set. (i) Only (ii) Only Both (i) and (ii) None of the options
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
by
Lakshman Patel RJIT
3.7k
views
nielit2017dec-scientistb
co-and-architecture
addressing-modes
instruction-format
0
votes
0
votes
4
answers
3
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
1,111
views
NIELIT 2017 DEC Scientist B - Section B: 4
In a cache memory if total number of sets are ‘$s$’, then the set offset is: $2^8$ $\log_2s$ $s^2$ $s$
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
by
Lakshman Patel RJIT
1.1k
views
nielit2017dec-scientistb
co-and-architecture
cache-memory
3
votes
3
votes
5
answers
4
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
2,991
views
NIELIT 2017 DEC Scientist B - Section B: 13
Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implementing the pipelining the machine adds $\text{5 ns}$ of overhead to each stage ... What is the speed up factor of the pipelining system (ignoring any hazard impact)? $7$ $14$ $3.11$ $6.22$
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
by
Lakshman Patel RJIT
3.0k
views
nielit2017dec-scientistb
co-and-architecture
pipelining
Subscribe to GATE CSE 2023 Test Series
Subscribe to GO Classes for GATE CSE 2023
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Recruitment of Scientific Officers in the Department of Atomic Energy 2023
GATE CSE 2023 Paper & Analysis - Memory Based
From GATE to Australia
DRDO Previous Year Papers
From Rank 4200 to 64: My Journey to Success in GATE CSE Exam
Subjects
All categories
General Aptitude
(2.5k)
Engineering Mathematics
(9.3k)
Digital Logic
(3.3k)
Programming and DS
(5.9k)
Algorithms
(4.6k)
Theory of Computation
(6.7k)
Compiler Design
(2.3k)
Operating System
(5.0k)
Databases
(4.6k)
CO and Architecture
(3.8k)
Computer Networks
(4.6k)
Non GATE
(1.3k)
Others
(2.4k)
Admissions
(649)
Exam Queries
(842)
Tier 1 Placement Questions
(17)
Job Queries
(75)
Projects
(9)
Unknown Category
(853)
Recent Blog Comments
1200/1000 = 1.2
Aptitude- 1- there was a question, Like in a...
Suppose typing happens at 1 keystroke per second....
The algorithm for graph colouring was to pick...
@Aakash_Bhardwaj all the best bro . For your...
Twitter
WhatsApp
Facebook
Reddit
LinkedIn
Email
Link Copied!
Copy