We assume that each stage takes ‘T’ unit of time both in pipelined and non-pipelined CPU.
Let total stages in pipelined CPU = Total stages in non-pipelined CPU = K
number of Instructions = N = 1
Pipelined CPU :
Total time (T1) = (K + (N – 1)) * T = KT
Non-Pipelined CPU :
Total time (T2) = KNT = KT
Considering buffer delays in pipelined CPU
Pipeline system contains interstage buffers registers that leads to delay if only one instructions we have to execute.
But in non-pipeline system we have no such registers so for only one instructions it will give better performance.
T1 > T2
IF buffer delay is negligible in pipeline then T1=T2
so over all T1$\geqslant$T2
Thus, option (B) is the answer.