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Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ?

  1. $T1=T2$
  2. $T1>T2$
  3. $T1<T2$
  4. $T1$ is $T2$ plus time taken for one instruction fetch cycle
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We assume that each stage takes ‘T’ unit of time both in pipelined and non-pipelined CPU.


Let total stages in pipelined CPU = Total stages in non-pipelined CPU = K 

 number of Instructions = N = 1

Pipelined CPU :

Total time (T1) = (K + (N – 1)) * T = KT

Non-Pipelined CPU :

Total time (T2) = KNT = KT

Considering buffer delays in pipelined CPU

Pipeline system contains interstage buffers registers that leads to delay if only one instructions we have to execute.

But in non-pipeline system we have no such registers so for only one instructions it will give better performance.

 T1 > T2

IF buffer delay is negligible in pipeline then T1=T2

so over all T1$\geqslant$T2

 Thus, option (B) is the answer.

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Pipelined CPUs are having interstage buffers that lead to additional delay. Therefore option B is correct.

T1>T2
Answer:

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