1 votes 1 votes If a clock with time period $“T”$ is used with $n$ stage shift register, then output of final stage will be delayed by $nT$ sec $(n-1)T$ sec $n/T$ sec $(2n-1)T$ sec Digital Logic nielit2016mar-scientistc digital-logic sequential-circuit + – admin asked Apr 2, 2020 • recategorized Oct 28, 2020 by Krithiga2101 admin 1.3k views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
1 votes 1 votes ANS : B (n−1)T(n−1)T sec anjli answered Feb 6, 2021 anjli comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes take 4 register and initial data is 1011 ans bit are moving from MSB to LSB 1'st 2'nd 3'rd 4'rt 1 0 1 1 -initial data 1 1 0 1 -first shift 1 1 1 0 -second shift 0 1 1 1 -third shift 1 0 1 1 -initial data option B n-1 shift required Mohit Kumar 6 answered May 3, 2020 Mohit Kumar 6 comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes Ans b is correct Because shift register Serial output n-1 times required A_dhruvpatel answered Nov 3, 2020 A_dhruvpatel comment Share Follow See all 0 reply Please log in or register to add a comment.